MIPS 54条多周期CPU.zip
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所属分类:课程资源 > 嵌入式
文件大小:26.94 MB
上传日期:2020-01-31 17:45
MD5:fd8d2c95a9************a7ad912be9
资源说明:计算机组成原理大作业,实验过程中实现了:54条指令的多周期MIPS指令集CPU的设计。
移动页面: MIP AMP

[资源合计] 文件夹:109,文件:539

# 文件名称 大小 最后修改时间
1 project_cpu54\project_cpu54.sim\sim_1\synth\timing\msim\xil_defaultlib\_lib1_0.qpg 25.63 MB 2018/7/18 22:25:40
2 project_cpu54\project_cpu54.sim\sim_1\impl\func\msim\xil_defaultlib\_lib1_0.qpg 25.52 MB 2018/6/14 0:35:30
3 project_cpu54\project_cpu54.sim\sim_1\synth\func\msim\xil_defaultlib\_lib1_0.qpg 23.8 MB 2018/6/19 23:51:45
4 project_cpu54\project_cpu54.sim\sim_1\synth\timing\tb_time_synth.sdf 18.17 MB 2018/7/18 22:25:33
5 project_cpu54\project_cpu54.sim\sim_1\impl\func\msim\xil_defaultlib\_lib1_0.qtl 13.17 MB 2018/6/14 0:35:30
6 project_cpu54\project_cpu54.sim\sim_1\synth\timing\msim\xil_defaultlib\_lib1_0.qtl 5.19 MB 2018/7/18 22:25:40
7 project_cpu54\project_cpu54.sim\sim_1\impl\func\tb_func_impl.v 4.54 MB 2018/6/14 0:35:13
8 project_cpu54\project_cpu54.sim\sim_1\synth\timing\tb_time_synth.v 3.72 MB 2018/7/18 22:25:23
9 project_cpu54\project_cpu54.sim\sim_1\behav\result.txt 3.47 MB 2018/7/17 23:55:28
10 project_cpu54\project_cpu54.sim\sim_1\synth\func\tb_func_synth.v 3.19 MB 2018/6/19 23:51:37
11 project_cpu54\project_cpu54.runs\impl_1\sccomp_dataflow_placed.dcp 3.1 MB 2018/6/14 16:58:38
12 project_cpu54\project_cpu54.runs\impl_1\sccomp_dataflow.dcp 2.25 MB 2018/6/14 16:56:27
13 project_cpu54\project_cpu54.runs\impl_1\sccomp_dataflow_opt.dcp 2.2 MB 2018/6/14 16:57:41
14 project_cpu54\project_cpu54.sim\sim_1\synth\timing\simulate.log 1.81 MB 2018/7/18 22:31:02
15 project_cpu54\project_cpu54.sim\sim_1\synth\timing\tb_time_synth.sdf_typ.csd 1.66 MB 2018/7/18 22:26:01
16 project_cpu54\project_cpu54.sim\sim_1\synth\func\msim\xil_defaultlib\_lib1_0.qtl 1.66 MB 2018/6/19 23:51:45
17 project_cpu54\project_cpu54.runs\synth_1\sccomp_dataflow.dcp 1.53 MB 2018/6/21 0:03:43
18 project_cpu54\project_cpu54.sim\sim_1\behav\msim\xil_defaultlib\_lib1_0.qpg 1.19 MB 2018/7/17 23:54:56
19 project_cpu54\project_cpu54.sim\sim_1\impl\func\msim\xil_defaultlib\_lib.qdb 1.05 MB 2018/6/14 0:35:30
20 project_cpu54\timing_report.txt 638.85 KB 2018/6/21 0:04:30
21 project_cpu54\project_cpu54.sim\sim_1\impl\func\msim\xil_defaultlib\_lib1_0.qdb 472 KB 2018/6/14 0:35:30
22 project_cpu54\project_cpu54.sim\sim_1\impl\func\msim\xil_defaultlib\_info 360.66 KB 2018/6/14 0:35:30
23 project_cpu54\project_cpu54.sim\sim_1\behav\msim\xil_defaultlib\_lib1_0.qtl 324.66 KB 2018/7/17 23:54:56
24 project_cpu54\project_cpu54.sim\sim_1\synth\timing\msim\xil_defaultlib\_lib.qdb 288 KB 2018/7/18 22:25:40
25 project_cpu54\project_cpu54.srcs\sources_1\ip\divider\divider.xml 265.59 KB 2018/6/20 23:59:55
26 project_cpu54\project_cpu54.sim\sim_1\synth\timing\msim\xil_defaultlib\_lib1_0.qdb 224 KB 2018/7/18 22:25:40
27 project_cpu54\project_cpu54.runs\synth_1\vivado.pb 213.29 KB 2018/6/21 0:03:44
28 project_cpu54\project_cpu54.srcs\sources_1\ip\dmem\dmem_sim_netlist.vhdl 177.87 KB 2018/6/3 16:26:29
29 project_cpu54\project_cpu54.srcs\sources_1\ip\dmem\dist_mem_gen_v8_0_10\hdl\dist_mem_gen_v8_0_vhsyn_rfs.vhd 169.08 KB 2018/6/3 16:25:46
30 project_cpu54\project_cpu54.srcs\sources_1\ip\imem\dist_mem_gen_v8_0_10\hdl\dist_mem_gen_v8_0_vhsyn_rfs.vhd 169.08 KB 2018/7/18 22:22:31
31 project_cpu54\vivado_pid1524.str 168.65 KB 2018/6/14 0:08:57
32 project_cpu54\project_cpu54.sim\sim_1\synth\func\msim\xil_defaultlib\_lib.qdb 160 KB 2018/6/19 23:51:45
33 project_cpu54\project_cpu54.sim\sim_1\synth\func\msim\xil_defaultlib\_lib1_0.qdb 160 KB 2018/6/19 23:51:45
34 project_cpu54\project_cpu54.sim\sim_1\behav\msim\dist_mem_gen_v8_0_10\_lib1_0.qpg 152 KB 2018/7/17 23:54:55
35 project_cpu54\project_cpu54.srcs\sources_1\ip\dmem\dmem_sim_netlist.v 133.14 KB 2018/6/3 16:26:29
36 project_cpu54\project_cpu54.runs\dmem_synth_1\dmem.dcp 129.68 KB 2018/6/3 16:26:29
37 project_cpu54\project_cpu54.srcs\sources_1\ip\dmem\dmem.dcp 129.68 KB 2018/6/3 16:26:29
38 project_cpu54\project_cpu54.runs\synth_1\runme.log 124.95 KB 2018/6/21 0:03:44
39 project_cpu54\project_cpu54.runs\synth_1\sccomp_dataflow.vds 123.78 KB 2018/6/21 0:03:44
40 project_cpu54\project_cpu54.sim\sim_1\synth\timing\vsim.wlf 120 KB 2018/7/18 22:31:00
41 project_cpu54\project_cpu54.sim\sim_1\behav\modelsim.ini 104.74 KB 2018/7/17 23:54:54
42 project_cpu54\project_cpu54.sim\sim_1\impl\func\modelsim.ini 104.74 KB 2018/6/14 0:35:17
43 project_cpu54\project_cpu54.sim\sim_1\synth\func\modelsim.ini 104.74 KB 2018/6/19 23:51:42
44 project_cpu54\project_cpu54.sim\sim_1\synth\timing\modelsim.ini 104.74 KB 2018/7/18 22:25:37
45 project_cpu54\project_cpu54.sim\sim_1\impl\func\simulate.log 100.31 KB 2018/6/14 0:36:21
46 project_cpu54\project_cpu54.sim\sim_1\impl\func\compile.log 92.95 KB 2018/6/14 0:35:30
47 project_cpu54\project_cpu54.sim\sim_1\synth\timing\msim\xil_defaultlib\_info 81.09 KB 2018/7/18 22:25:40
48 project_cpu54\project_cpu54.runs\impl_1\sccomp_dataflow_io_placed.rpt 80.43 KB 2018/6/14 16:58:38
49 project_cpu54\project_cpu54.srcs\sources_1\ip\divider\divider.xci 72.6 KB 2018/6/20 23:58:56
50 project_cpu54\project_cpu54.runs\dmem_synth_1\vivado.pb 58.19 KB 2018/6/3 16:26:29
51 project_cpu54\project_cpu54.srcs\sources_1\ip\dmem\dmem.xml 53.1 KB 2018/6/3 16:26:32
52 project_cpu54\vivado.log 51.33 KB 2018/7/18 22:31:16
53 project_cpu54\vivado_7828.backup.log 51.33 KB 2018/7/18 22:31:16
54 project_cpu54\project_cpu54.srcs\sources_1\ip\imem\imem.xml 50.65 KB 2018/7/18 22:22:31
55 project_cpu54\project_cpu54.sim\sim_1\behav\msim\dist_mem_gen_v8_0_10\_lib.qdb 48 KB 2018/7/17 23:54:55
56 project_cpu54\project_cpu54.sim\sim_1\behav\msim\xil_defaultlib\_lib.qdb 48 KB 2018/7/17 23:54:56
57 project_cpu54\project_cpu54.sim\sim_1\behav\msim\xpm\_lib.qdb 48 KB 2018/7/17 23:54:54
58 project_cpu54\project_cpu54.sim\sim_1\behav\vsim.wlf 48 KB 2018/7/17 23:55:28
59 project_cpu54\project_cpu54.sim\sim_1\impl\func\vsim.wlf 48 KB 2018/6/14 0:36:19
60 project_cpu54\project_cpu54.sim\sim_1\synth\func\vsim.wlf 48 KB 2018/6/20 0:15:29
61 project_cpu54\project_cpu54.ip_user_files\mem_init_files\imem.mif 46.25 KB 2018/7/18 22:25:33
62 project_cpu54\project_cpu54.ip_user_files\sim_scripts\imem\activehdl\imem.mif 46.25 KB 2018/7/18 22:22:33
63 project_cpu54\project_cpu54.ip_user_files\sim_scripts\imem\ies\imem.mif 46.25 KB 2018/7/18 22:22:33
64 project_cpu54\project_cpu54.ip_user_files\sim_scripts\imem\modelsim\imem.mif 46.25 KB 2018/7/18 22:22:32
65 project_cpu54\project_cpu54.ip_user_files\sim_scripts\imem\questa\imem.mif 46.25 KB 2018/7/18 22:22:33
66 project_cpu54\project_cpu54.ip_user_files\sim_scripts\imem\riviera\imem.mif 46.25 KB 2018/7/18 22:22:33
67 project_cpu54\project_cpu54.ip_user_files\sim_scripts\imem\vcs\imem.mif 46.25 KB 2018/7/18 22:22:33
68 project_cpu54\project_cpu54.ip_user_files\sim_scripts\imem\xsim\imem.mif 46.25 KB 2018/7/18 22:22:32
69 project_cpu54\project_cpu54.sim\sim_1\behav\imem.mif 46.25 KB 2018/7/17 23:54:49
70 project_cpu54\project_cpu54.sim\sim_1\synth\func\imem.mif 46.25 KB 2018/6/19 23:51:37
71 project_cpu54\project_cpu54.sim\sim_1\synth\timing\imem.mif 46.25 KB 2018/7/18 22:25:33
72 project_cpu54\project_cpu54.srcs\sources_1\ip\imem\imem.mif 46.25 KB 2018/7/18 22:22:31
73 project_cpu54\project_cpu54.sim\sim_1\impl\func\imem.mif 42.35 KB 2018/6/14 0:35:13
74 project_cpu54\project_cpu54.sim\sim_1\synth\func\msim\xil_defaultlib\_info 38.64 KB 2018/6/19 23:51:45
75 project_cpu54\project_cpu54.runs\Divider_synth_1\vivado.pb 37.46 KB 2018/6/20 23:59:53
76 project_cpu54\vivado_12788.backup.log 36.89 KB 2018/7/17 23:56:26
77 project_cpu54\project_cpu54.runs\dmem_synth_1\runme.log 34.69 KB 2018/6/3 16:26:30
78 project_cpu54\project_cpu54.runs\dmem_synth_1\dmem.vds 34.53 KB 2018/6/3 16:26:29
79 project_cpu54\project_cpu54.sim\sim_1\behav\msim\dist_mem_gen_v8_0_10\_lib1_0.qdb 32 KB 2018/7/17 23:54:55
80 project_cpu54\project_cpu54.sim\sim_1\behav\msim\xil_defaultlib\_lib1_0.qdb 32 KB 2018/7/17 23:54:56
81 project_cpu54\project_cpu54.sim\sim_1\behav\msim\xpm\_lib1_0.qdb 32 KB 2018/7/17 23:54:54
82 project_cpu54\project_cpu54.sim\sim_1\behav\msim\xpm\_lib1_0.qpg 32 KB 2018/7/17 23:54:54
83 project_cpu54\project_cpu54.ip_user_files\ipstatic\clk_wiz_v5_3_1\mmcm_pll_drp_func_7s_mmcm.vh 23.67 KB 2018/6/13 23:18:17
84 project_cpu54\project_cpu54.srcs\sources_1\ip\divider\clk_wiz_v5_3_1\mmcm_pll_drp_func_7s_mmcm.vh 23.67 KB 2018/6/20 23:58:58
85 project_cpu54\project_cpu54.ip_user_files\ipstatic\clk_wiz_v5_3_1\mmcm_pll_drp_func_us_mmcm.vh 23.66 KB 2018/6/13 23:18:17
86 project_cpu54\project_cpu54.srcs\sources_1\ip\divider\clk_wiz_v5_3_1\mmcm_pll_drp_func_us_mmcm.vh 23.66 KB 2018/6/20 23:58:58
87 project_cpu54\project_cpu54.runs\Divider_synth_1\divider.vds 23.19 KB 2018/6/20 23:59:53
88 project_cpu54\project_cpu54.runs\Divider_synth_1\runme.log 23.15 KB 2018/6/20 23:59:54
89 project_cpu54\project_cpu54.ip_user_files\ipstatic\clk_wiz_v5_3_1\mmcm_pll_drp_func_us_pll.vh 21.54 KB 2018/6/13 23:18:17
90 project_cpu54\project_cpu54.srcs\sources_1\ip\divider\clk_wiz_v5_3_1\mmcm_pll_drp_func_us_pll.vh 21.54 KB 2018/6/20 23:58:58
91 project_cpu54\project_cpu54.sim\sim_1\synth\timing\compile.log 19.67 KB 2018/7/18 22:25:42
92 project_cpu54\vivado_10952.backup.log 19.66 KB 2018/7/16 16:43:41
93 project_cpu54\project_cpu54.ip_user_files\ipstatic\clk_wiz_v5_3_1\mmcm_pll_drp_func_7s_pll.vh 18.59 KB 2018/6/13 23:18:17
94 project_cpu54\project_cpu54.srcs\sources_1\ip\divider\clk_wiz_v5_3_1\mmcm_pll_drp_func_7s_pll.vh 18.59 KB 2018/6/20 23:58:58
95 project_cpu54\project_cpu54.srcs\sources_1\new\cpu54.v 17.51 KB 2018/6/18 22:47:07
96 project_cpu54\project_cpu54.srcs\sources_1\ip\dmem\dist_mem_gen_v8_0_10\hdl\dist_mem_gen_v8_0.vhd 17.31 KB 2018/6/3 16:25:46
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98 project_cpu54\project_cpu54.runs\impl_1\place_design.pb 17.27 KB 2018/6/14 16:58:38
99 project_cpu54\project_cpu54.sim\sim_1\behav\msim\dist_mem_gen_v8_0_10\_lib1_0.qtl 17.19 KB 2018/7/17 23:54:55
100 project_cpu54\project_cpu54.runs\impl_1\sccomp_dataflow_control_sets_placed.rpt 17.09 KB 2018/6/14 16:58:38
101 project_cpu54\project_cpu54.xpr 16.48 KB 2018/7/18 22:25:22
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105 project_cpu54\vivado_19764.backup.log 14.96 KB 2018/6/21 0:05:26
106 project_cpu54\project_cpu54.runs\impl_1\sccomp_dataflow.vdi 14.68 KB 2018/6/14 16:58:51
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108 project_cpu54\project_cpu54.ip_user_files\mem_init_files\mips_54_mars_board_switch_student.coe 14.08 KB 2018/7/18 22:25:33
109 project_cpu54\project_cpu54.ip_user_files\sim_scripts\imem\activehdl\mips_54_mars_board_switch_student.coe 14.08 KB 2018/7/18 22:22:33
110 project_cpu54\project_cpu54.ip_user_files\sim_scripts\imem\ies\mips_54_mars_board_switch_student.coe 14.08 KB 2018/7/18 22:22:33
111 project_cpu54\project_cpu54.ip_user_files\sim_scripts\imem\modelsim\mips_54_mars_board_switch_student.coe 14.08 KB 2018/7/18 22:22:32
112 project_cpu54\project_cpu54.ip_user_files\sim_scripts\imem\questa\mips_54_mars_board_switch_student.coe 14.08 KB 2018/7/18 22:22:33
113 project_cpu54\project_cpu54.ip_user_files\sim_scripts\imem\riviera\mips_54_mars_board_switch_student.coe 14.08 KB 2018/7/18 22:22:33
114 project_cpu54\project_cpu54.ip_user_files\sim_scripts\imem\vcs\mips_54_mars_board_switch_student.coe 14.08 KB 2018/7/18 22:22:33
115 project_cpu54\project_cpu54.ip_user_files\sim_scripts\imem\xsim\mips_54_mars_board_switch_student.coe 14.08 KB 2018/7/18 22:22:32
116 project_cpu54\project_cpu54.sim\sim_1\behav\mips_54_mars_board_switch_student.coe 14.08 KB 2018/7/17 23:54:49
117 project_cpu54\project_cpu54.sim\sim_1\synth\func\mips_54_mars_board_switch_student.coe 14.08 KB 2018/6/19 23:51:37
118 project_cpu54\project_cpu54.sim\sim_1\synth\timing\mips_54_mars_board_switch_student.coe 14.08 KB 2018/7/18 22:25:33
119 project_cpu54\project_cpu54.sim\sim_1\impl\func\mips_54_mars_board_switch_student.coe 12.9 KB 2018/6/14 0:35:13
120 project_cpu54\project_cpu54.runs\impl_1\gen_run.xml 12.35 KB 2018/6/14 16:56:27
121 project_cpu54\project_cpu54.sim\sim_1\behav\msim\xil_defaultlib\_info 12.25 KB 2018/7/17 23:54:56
122 project_cpu54\project_cpu54.sim\sim_1\synth\func\simulate.log 12.02 KB 2018/6/20 0:15:35
123 project_cpu54\project_cpu54.runs\Divider_synth_1\divider.dcp 11.72 KB 2018/6/20 23:59:53
124 project_cpu54\project_cpu54.srcs\sources_1\ip\divider\divider.dcp 11.72 KB 2018/6/20 23:59:53
125 project_cpu54\project_cpu54.srcs\sources_1\ip\imem\imem.xci 11.12 KB 2018/6/17 17:24:06
126 project_cpu54\project_cpu54.srcs\sources_1\ip\dmem\dmem.xci 10.89 KB 2018/6/3 16:24:23
127 project_cpu54\project_cpu54.sim\sim_1\synth\func\compile.log 10.02 KB 2018/6/19 23:51:46
128 project_cpu54\project_cpu54.runs\impl_1\sccomp_dataflow_utilization_placed.rpt 9.4 KB 2018/6/14 16:58:38
129 project_cpu54\project_cpu54.srcs\sim_1\new\tb.v 7.97 KB 2018/7/18 22:25:19
130 project_cpu54\project_cpu54.runs\synth_1\gen_run.xml 7.71 KB 2018/7/18 22:25:22
131 project_cpu54\project_cpu54.runs\synth_1\sccomp_dataflow_utilization_synth.rpt 7.29 KB 2018/6/21 0:03:44
132 project_cpu54\project_cpu54.runs\Divider_synth_1\divider_utilization_synth.rpt 7.25 KB 2018/6/20 23:59:53
133 project_cpu54\project_cpu54.runs\Divider_synth_1\ISEWrap.js 7.14 KB 2018/6/20 23:59:00
134 project_cpu54\project_cpu54.runs\dmem_synth_1\ISEWrap.js 7.14 KB 2018/6/3 16:25:47
135 project_cpu54\project_cpu54.runs\impl_1\ISEWrap.js 7.14 KB 2018/6/14 16:56:27
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139 project_cpu54\project_cpu54.srcs\sources_1\ip\divider\divider_sim_netlist.vhdl 6.91 KB 2018/6/20 23:59:53
140 project_cpu54\project_cpu54.sim\sim_1\behav\compile.log 6.82 KB 2018/7/17 23:54:56
141 project_cpu54\project_cpu54.srcs\sources_1\new\MULT.v 6.75 KB 2018/6/3 15:26:58
142 project_cpu54\project_cpu54.runs\dmem_synth_1\dmem_utilization_synth.rpt 6.7 KB 2018/6/3 16:26:29
143 project_cpu54\project_cpu54.ip_user_files\sim_scripts\divider\vcs\divider.sh 6.69 KB 2018/6/20 23:59:04
144 project_cpu54\project_cpu54.srcs\sources_1\ip\divider\divider_clk_wiz.v 6.67 KB 2018/6/20 23:58:58
145 project_cpu54\project_cpu54.srcs\sources_1\ip\dmem\synth\dmem.vhd 6.67 KB 2018/6/3 16:25:46
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148 project_cpu54\project_cpu54.srcs\sources_1\new\MULTU.v 6.56 KB 2018/6/3 15:26:58
149 project_cpu54\project_cpu54.ip_user_files\sim_scripts\dmem\vcs\dmem.sh 6.36 KB 2018/6/3 16:25:48
150 project_cpu54\project_cpu54.ip_user_files\sim_scripts\divider\ies\divider.sh 5.42 KB 2018/6/20 23:59:04
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153 project_cpu54\project_cpu54.srcs\sources_1\ip\divider\doc\clk_wiz_v5_3_changelog.txt 5.26 KB 2018/6/20 23:58:59
154 project_cpu54\project_cpu54.cache\wt\synthesis.wdf 5.13 KB 2018/6/21 0:03:41
155 project_cpu54\project_cpu54.runs\impl_1\opt_design.pb 4.88 KB 2018/6/14 16:57:45
156 project_cpu54\project_cpu54.cache\wt\webtalk_pa.xml 4.79 KB 2018/7/18 22:31:14
157 project_cpu54\project_cpu54.ip_user_files\sim_scripts\divider\questa\divider.sh 4.59 KB 2018/6/20 23:59:03
158 project_cpu54\project_cpu54.ip_user_files\sim_scripts\dmem\questa\dmem.sh 4.55 KB 2018/6/3 16:25:48
159 project_cpu54\project_cpu54.ip_user_files\sim_scripts\imem\questa\imem.sh 4.55 KB 2018/7/18 22:22:32
160 project_cpu54\project_cpu54.sim\sim_1\behav\msim\xpm\_lib1_0.qtl 4.53 KB 2018/7/17 23:54:54
161 project_cpu54\project_cpu54.ip_user_files\sim_scripts\divider\modelsim\divider.sh 4.48 KB 2018/6/20 23:59:03
162 project_cpu54\project_cpu54.ip_user_files\sim_scripts\dmem\modelsim\dmem.sh 4.44 KB 2018/6/3 16:25:48
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164 project_cpu54\project_cpu54.srcs\sim_1\new\test_tb.v 4.32 KB 2018/6/2 18:59:57
165 project_cpu54\project_cpu54.runs\synth_1\sccomp_dataflow.tcl 4.18 KB 2018/6/21 0:00:16
166 project_cpu54\project_cpu54.ip_user_files\sim_scripts\divider\activehdl\divider.sh 4.18 KB 2018/6/20 23:59:04
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