risc-v core Verilog源码.7z
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所属分类:开发技术 > 硬件开发
文件大小:2.69 MB
上传日期:2020-02-08 10:13
MD5:3c1603e762************f8b004e668
资源说明:risc-v core的Verilog源码,基于Verilog的 RISC CPU设计。
移动页面: MIP AMP

[资源合计] 文件夹:11,文件:293

# 文件名称 大小 最后修改时间
1 sifive_E51_coreplex_rtl_evaluation_v1p0\verilog\testbench\_EVAL_62_sim.v 8.71 MB 2017/5/4 20:26:13
2 sifive_E51_coreplex_rtl_evaluation_v1p0\verilog\design\_EVAL_62.v 5.89 MB 2017/5/4 20:26:10
3 sifive_E51_coreplex_rtl_evaluation_v1p0\verilog\design\_EVAL_48.v 2.47 MB 2017/5/4 20:26:10
4 sifive_E51_coreplex_rtl_evaluation_v1p0\verilog\testbench\_EVAL_48_sim.v 1.88 MB 2017/5/4 20:26:11
5 sifive_E51_coreplex_rtl_evaluation_v1p0\verilog\design\E51_ECoreplexIP_system.v 346.36 KB 2017/5/4 20:26:08
6 sifive_E51_coreplex_rtl_evaluation_v1p0\verilog\design\_EVAL_143.v 331.75 KB 2017/5/4 20:26:09
7 sifive_E51_coreplex_rtl_evaluation_v1p0\verilog\design\_EVAL_107.v 204 KB 2017/5/4 20:26:09
8 sifive_E51_coreplex_rtl_evaluation_v1p0\verilog\design\_EVAL_94.v 195.54 KB 2017/5/4 20:26:11
9 sifive_E51_coreplex_rtl_evaluation_v1p0\verilog\testbench\_EVAL_143_sim.v 194.2 KB 2017/5/4 20:26:11
10 sifive_E51_coreplex_rtl_evaluation_v1p0\verilog\testbench\E51_ECoreplexIP_system_sim.v 174.91 KB 2017/5/4 20:26:11
11 sifive_E51_coreplex_rtl_evaluation_v1p0\verilog\design\_EVAL_87.v 173.93 KB 2017/5/4 20:26:10
12 sifive_E51_coreplex_rtl_evaluation_v1p0\verilog\design\_EVAL_111.v 154.25 KB 2017/5/4 20:26:09
13 sifive_E51_coreplex_rtl_evaluation_v1p0\verilog\design\_EVAL_112.v 130.29 KB 2017/5/4 20:26:09
14 sifive_E51_coreplex_rtl_evaluation_v1p0\verilog\testbench\_EVAL_140.v 125.82 KB 2017/5/4 20:26:11
15 sifive_E51_coreplex_rtl_evaluation_v1p0\verilog\testbench\_EVAL_118.v 125.82 KB 2017/5/4 20:26:11
16 sifive_E51_coreplex_rtl_evaluation_v1p0\verilog\testbench\_EVAL_141.v 125.74 KB 2017/5/4 20:26:11
17 sifive_E51_coreplex_rtl_evaluation_v1p0\verilog\design\_EVAL_92.v 105.1 KB 2017/5/4 20:26:11
18 sifive_E51_coreplex_rtl_evaluation_v1p0\verilog\design\_EVAL_85.v 105.07 KB 2017/5/4 20:26:10
19 sifive_E51_coreplex_rtl_evaluation_v1p0\verilog\testbench\TLPortRAMSlave_testRAM.v 94.2 KB 2017/5/4 20:26:13
20 sifive_E51_coreplex_rtl_evaluation_v1p0\verilog\design\_EVAL_93.v 90.36 KB 2017/5/4 20:26:11
21 sifive_E51_coreplex_rtl_evaluation_v1p0\verilog\design\_EVAL_104.v 75.57 KB 2017/5/4 20:26:09
22 sifive_E51_coreplex_rtl_evaluation_v1p0\verilog\testbench\TLMonitor_54.v 74.48 KB 2017/5/4 20:26:13
23 sifive_E51_coreplex_rtl_evaluation_v1p0\verilog\testbench\TLMonitor_55.v 74.37 KB 2017/5/4 20:26:13
24 sifive_E51_coreplex_rtl_evaluation_v1p0\verilog\testbench\TLMonitor_56.v 73.48 KB 2017/5/4 20:26:13
25 sifive_E51_coreplex_rtl_evaluation_v1p0\verilog\testbench\TLMonitor_57.v 73.48 KB 2017/5/4 20:26:13
26 sifive_E51_coreplex_rtl_evaluation_v1p0\verilog\testbench\_EVAL_88.v 63.37 KB 2017/5/4 20:26:13
27 sifive_E51_coreplex_rtl_evaluation_v1p0\verilog\testbench\_EVAL_90.v 63.28 KB 2017/5/4 20:26:13
28 sifive_E51_coreplex_rtl_evaluation_v1p0\verilog\testbench\_EVAL_96.v 63.27 KB 2017/5/4 20:26:13
29 sifive_E51_coreplex_rtl_evaluation_v1p0\verilog\testbench\_EVAL_24.v 62.82 KB 2017/5/4 20:26:11
30 sifive_E51_coreplex_rtl_evaluation_v1p0\verilog\testbench\_EVAL_27.v 62.81 KB 2017/5/4 20:26:11
31 sifive_E51_coreplex_rtl_evaluation_v1p0\verilog\testbench\_EVAL_5.v 62.8 KB 2017/5/4 20:26:11
32 sifive_E51_coreplex_rtl_evaluation_v1p0\verilog\testbench\_EVAL_144.v 62.77 KB 2017/5/4 20:26:11
33 sifive_E51_coreplex_rtl_evaluation_v1p0\verilog\testbench\_EVAL_28.v 62.75 KB 2017/5/4 20:26:11
34 sifive_E51_coreplex_rtl_evaluation_v1p0\verilog\testbench\_EVAL_20.v 62.66 KB 2017/5/4 20:26:11
35 sifive_E51_coreplex_rtl_evaluation_v1p0\verilog\testbench\_EVAL_18.v 62.66 KB 2017/5/4 20:26:11
36 sifive_E51_coreplex_rtl_evaluation_v1p0\verilog\testbench\_EVAL_8.v 62.64 KB 2017/5/4 20:26:13
37 sifive_E51_coreplex_rtl_evaluation_v1p0\verilog\testbench\_EVAL_25.v 62 KB 2017/5/4 20:26:11
38 sifive_E51_coreplex_rtl_evaluation_v1p0\verilog\testbench\_EVAL_142.v 61.57 KB 2017/5/4 20:26:11
39 sifive_E51_coreplex_rtl_evaluation_v1p0\verilog\testbench\_EVAL_100.v 61.55 KB 2017/5/4 20:26:11
40 sifive_E51_coreplex_rtl_evaluation_v1p0\verilog\testbench\_EVAL_122.v 61.54 KB 2017/5/4 20:26:11
41 sifive_E51_coreplex_rtl_evaluation_v1p0\verilog\design\_EVAL_19.v 61.45 KB 2017/5/4 20:26:09
42 sifive_E51_coreplex_rtl_evaluation_v1p0\verilog\testbench\_EVAL_70.v 61.21 KB 2017/5/4 20:26:13
43 sifive_E51_coreplex_rtl_evaluation_v1p0\verilog\design\_EVAL_4.v 61.12 KB 2017/5/4 20:26:10
44 sifive_E51_coreplex_rtl_evaluation_v1p0\verilog\testbench\_EVAL_101.v 60.76 KB 2017/5/4 20:26:11
45 sifive_E51_coreplex_rtl_evaluation_v1p0\verilog\testbench\_EVAL_12.v 60.75 KB 2017/5/4 20:26:11
46 sifive_E51_coreplex_rtl_evaluation_v1p0\verilog\testbench\_EVAL_13.v 60.74 KB 2017/5/4 20:26:11
47 sifive_E51_coreplex_rtl_evaluation_v1p0\verilog\testbench\_EVAL_71.v 60.57 KB 2017/5/4 20:26:13
48 sifive_E51_coreplex_rtl_evaluation_v1p0\verilog\testbench\_EVAL_74.v 60.42 KB 2017/5/4 20:26:13
49 sifive_E51_coreplex_rtl_evaluation_v1p0\verilog\testbench\_EVAL_66.v 60.36 KB 2017/5/4 20:26:13
50 sifive_E51_coreplex_rtl_evaluation_v1p0\verilog\testbench\_EVAL_75.v 59.75 KB 2017/5/4 20:26:13
51 sifive_E51_coreplex_rtl_evaluation_v1p0\verilog\testbench\_EVAL_45.v 59.74 KB 2017/5/4 20:26:11
52 sifive_E51_coreplex_rtl_evaluation_v1p0\verilog\testbench\_EVAL_58.v 59.71 KB 2017/5/4 20:26:11
53 sifive_E51_coreplex_rtl_evaluation_v1p0\verilog\testbench\_EVAL_67.v 59.7 KB 2017/5/4 20:26:13
54 sifive_E51_coreplex_rtl_evaluation_v1p0\verilog\testbench\_EVAL_53.v 59.68 KB 2017/5/4 20:26:11
55 sifive_E51_coreplex_rtl_evaluation_v1p0\verilog\testbench\_EVAL_157.v 59.55 KB 2017/5/4 20:26:11
56 sifive_E51_coreplex_rtl_evaluation_v1p0\verilog\testbench\_EVAL_160.v 59.3 KB 2017/5/4 20:26:11
57 sifive_E51_coreplex_rtl_evaluation_v1p0\verilog\testbench\_EVAL_164.v 59.27 KB 2017/5/4 20:26:11
58 sifive_E51_coreplex_rtl_evaluation_v1p0\verilog\testbench\_EVAL_162.v 59.26 KB 2017/5/4 20:26:11
59 sifive_E51_coreplex_rtl_evaluation_v1p0\verilog\testbench\_EVAL_148.v 59.23 KB 2017/5/4 20:26:11
60 sifive_E51_coreplex_rtl_evaluation_v1p0\verilog\testbench\_EVAL_151.v 59.23 KB 2017/5/4 20:26:11
61 sifive_E51_coreplex_rtl_evaluation_v1p0\verilog\testbench\_EVAL_52.v 59.05 KB 2017/5/4 20:26:11
62 sifive_E51_coreplex_rtl_evaluation_v1p0\verilog\testbench\_EVAL_158.v 58.77 KB 2017/5/4 20:26:11
63 sifive_E51_coreplex_rtl_evaluation_v1p0\verilog\testbench\_EVAL_152.v 58.72 KB 2017/5/4 20:26:11
64 sifive_E51_coreplex_rtl_evaluation_v1p0\verilog\testbench\_EVAL_168.v 58.3 KB 2017/5/4 20:26:11
65 sifive_E51_coreplex_rtl_evaluation_v1p0\verilog\testbench\_EVAL_169.v 57.59 KB 2017/5/4 20:26:11
66 sifive_E51_coreplex_rtl_evaluation_v1p0\verilog\testbench\_EVAL_35.v 56.6 KB 2017/5/4 20:26:11
67 sifive_E51_coreplex_rtl_evaluation_v1p0\verilog\testbench\_EVAL_34.v 56.53 KB 2017/5/4 20:26:11
68 sifive_E51_coreplex_rtl_evaluation_v1p0\verilog\design\_EVAL_14.v 53.99 KB 2017/5/4 20:26:09
69 sifive_E51_coreplex_rtl_evaluation_v1p0\verilog\testbench\_EVAL_112_sim.v 46.37 KB 2017/5/4 20:26:11
70 sifive_E51_coreplex_rtl_evaluation_v1p0\verilog\design\_EVAL_126.v 46.19 KB 2017/5/4 20:26:09
71 sifive_E51_coreplex_rtl_evaluation_v1p0\verilog\testbench\_EVAL_15_sim.v 45.14 KB 2017/5/4 20:26:11
72 sifive_E51_coreplex_rtl_evaluation_v1p0\verilog\design\_EVAL_95.v 43.37 KB 2017/5/4 20:26:11
73 sifive_E51_coreplex_rtl_evaluation_v1p0\verilog\design\_EVAL_105.v 42.1 KB 2017/5/4 20:26:09
74 sifive_E51_coreplex_rtl_evaluation_v1p0\verilog\testbench\_EVAL_107_sim.v 40.3 KB 2017/5/4 20:26:11
75 sifive_E51_coreplex_rtl_evaluation_v1p0\verilog\design\_EVAL_47.v 39.7 KB 2017/5/4 20:26:09
76 sifive_E51_coreplex_rtl_evaluation_v1p0\verilog\design\_EVAL_15.v 39.45 KB 2017/5/4 20:26:09
77 sifive_E51_coreplex_rtl_evaluation_v1p0\verilog\testbench\_EVAL_14_sim.v 38.44 KB 2017/5/4 20:26:11
78 sifive_E51_coreplex_rtl_evaluation_v1p0\verilog\design\_EVAL_110.v 38.26 KB 2017/5/4 20:26:09
79 sifive_E51_coreplex_rtl_evaluation_v1p0\verilog\design\_EVAL_2.v 37.88 KB 2017/5/4 20:26:09
80 sifive_E51_coreplex_rtl_evaluation_v1p0\verilog\testbench\_EVAL_1_sim.v 35.36 KB 2017/5/4 20:26:11
81 sifive_E51_coreplex_rtl_evaluation_v1p0\verilog\testbench\_EVAL_47_sim.v 32.92 KB 2017/5/4 20:26:11
82 sifive_E51_coreplex_rtl_evaluation_v1p0\verilog\design\_EVAL_84.v 32.26 KB 2017/5/4 20:26:10
83 sifive_E51_coreplex_rtl_evaluation_v1p0\verilog\testbench\_EVAL_126_sim.v 31.66 KB 2017/5/4 20:26:11
84 sifive_E51_coreplex_rtl_evaluation_v1p0\verilog\design\_EVAL_1.v 31.43 KB 2017/5/4 20:26:09
85 sifive_E51_coreplex_rtl_evaluation_v1p0\verilog\testbench\TLXbar_xbar.v 30.4 KB 2017/5/4 20:26:13
86 sifive_E51_coreplex_rtl_evaluation_v1p0\verilog\testbench\_EVAL_30_sim.v 27.61 KB 2017/5/4 20:26:11
87 sifive_E51_coreplex_rtl_evaluation_v1p0\verilog\design\_EVAL_57.v 26.96 KB 2017/5/4 20:26:10
88 sifive_E51_coreplex_rtl_evaluation_v1p0\verilog\design\_EVAL_171.v 26.57 KB 2017/5/4 20:26:09
89 sifive_E51_coreplex_rtl_evaluation_v1p0\verilog\testbench\_EVAL_85_sim.v 26.14 KB 2017/5/4 20:26:13
90 sifive_E51_coreplex_rtl_evaluation_v1p0\verilog\testbench\_EVAL_92_sim.v 26.1 KB 2017/5/4 20:26:13
91 sifive_E51_coreplex_rtl_evaluation_v1p0\verilog\design\_EVAL_135.v 25.33 KB 2017/5/4 20:26:09
92 sifive_E51_coreplex_rtl_evaluation_v1p0\verilog\design\_EVAL_117.v 25.31 KB 2017/5/4 20:26:09
93 sifive_E51_coreplex_rtl_evaluation_v1p0\verilog\design\_EVAL_89.v 24.79 KB 2017/5/4 20:26:10
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95 sifive_E51_coreplex_rtl_evaluation_v1p0\verilog\design\_EVAL_180.v 23.98 KB 2017/5/4 20:26:09
96 sifive_E51_coreplex_rtl_evaluation_v1p0\verilog\testbench\_EVAL_87_sim.v 23.96 KB 2017/5/4 20:26:13
97 sifive_E51_coreplex_rtl_evaluation_v1p0\verilog\design\_EVAL_170.v 22.34 KB 2017/5/4 20:26:09
98 sifive_E51_coreplex_rtl_evaluation_v1p0\verilog\testbench\_EVAL_57_sim.v 21.93 KB 2017/5/4 20:26:11
99 sifive_E51_coreplex_rtl_evaluation_v1p0\verilog\design\_EVAL_139.v 21.36 KB 2017/5/4 20:26:09
100 sifive_E51_coreplex_rtl_evaluation_v1p0\verilog\design\_EVAL_106.v 19.75 KB 2017/5/4 20:26:09
101 sifive_E51_coreplex_rtl_evaluation_v1p0\verilog\design\_EVAL_59.v 19.4 KB 2017/5/4 20:26:10
102 sifive_E51_coreplex_rtl_evaluation_v1p0\verilog\testbench\TLFragmenter_sram.v 19.05 KB 2017/5/4 20:26:13
103 sifive_E51_coreplex_rtl_evaluation_v1p0\verilog\design\_EVAL_63.v 18.81 KB 2017/5/4 20:26:10
104 sifive_E51_coreplex_rtl_evaluation_v1p0\verilog\design\_EVAL_172.v 18.34 KB 2017/5/4 20:26:09
105 sifive_E51_coreplex_rtl_evaluation_v1p0\verilog\testbench\_EVAL_0_sim.v 17.63 KB 2017/5/4 20:26:11
106 sifive_E51_coreplex_rtl_evaluation_v1p0\verilog\design\_EVAL_33.v 17.21 KB 2017/5/4 20:26:09
107 sifive_E51_coreplex_rtl_evaluation_v1p0\verilog\testbench\_EVAL_111_sim.v 16.73 KB 2017/5/4 20:26:11
108 sifive_E51_coreplex_rtl_evaluation_v1p0\verilog\design\_EVAL_7.v 16.15 KB 2017/5/4 20:26:10
109 sifive_E51_coreplex_rtl_evaluation_v1p0\verilog\design\_EVAL_156.v 16.12 KB 2017/5/4 20:26:09
110 sifive_E51_coreplex_rtl_evaluation_v1p0\verilog\design\_EVAL_150.v 15.78 KB 2017/5/4 20:26:09
111 sifive_E51_coreplex_rtl_evaluation_v1p0\verilog\testbench\ECoreplexIPAllPortRAMTestHarness.v 15.77 KB 2017/5/4 20:26:11
112 sifive_E51_coreplex_rtl_evaluation_v1p0\verilog\design\_EVAL_69.v 15.71 KB 2017/5/4 20:26:10
113 sifive_E51_coreplex_rtl_evaluation_v1p0\verilog\design\_EVAL_65.v 15.71 KB 2017/5/4 20:26:10
114 sifive_E51_coreplex_rtl_evaluation_v1p0\verilog\design\_EVAL_73.v 15.7 KB 2017/5/4 20:26:10
115 sifive_E51_coreplex_rtl_evaluation_v1p0\verilog\design\_EVAL_31.v 15.4 KB 2017/5/4 20:26:09
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117 sifive_E51_coreplex_rtl_evaluation_v1p0\verilog\design\_EVAL_51.v 15.18 KB 2017/5/4 20:26:10
118 sifive_E51_coreplex_rtl_evaluation_v1p0\verilog\design\_EVAL_44.v 15.16 KB 2017/5/4 20:26:09
119 sifive_E51_coreplex_rtl_evaluation_v1p0\verilog\design\_EVAL_99.v 15.07 KB 2017/5/4 20:26:11
120 sifive_E51_coreplex_rtl_evaluation_v1p0\verilog\design\_EVAL_97.v 13.59 KB 2017/5/4 20:26:11
121 sifive_E51_coreplex_rtl_evaluation_v1p0\verilog\testbench\TLBuffer_sram.v 13.2 KB 2017/5/4 20:26:13
122 sifive_E51_coreplex_rtl_evaluation_v1p0\verilog\design\_EVAL_121.v 13.08 KB 2017/5/4 20:26:09
123 sifive_E51_coreplex_rtl_evaluation_v1p0\verilog\design\_EVAL_138.v 13.06 KB 2017/5/4 20:26:09
124 sifive_E51_coreplex_rtl_evaluation_v1p0\verilog\testbench\TLRAM_sram.v 12.71 KB 2017/5/4 20:26:13
125 sifive_E51_coreplex_rtl_evaluation_v1p0\verilog\design\_EVAL_163.v 12.49 KB 2017/5/4 20:26:09
126 sifive_E51_coreplex_rtl_evaluation_v1p0\verilog\design\_EVAL_109.v 12.07 KB 2017/5/4 20:26:09
127 sifive_E51_coreplex_rtl_evaluation_v1p0\verilog\design\_EVAL_161.v 11.58 KB 2017/5/4 20:26:09
128 sifive_E51_coreplex_rtl_evaluation_v1p0\verilog\testbench\_EVAL_95_sim.v 11.27 KB 2017/5/4 20:26:13
129 sifive_E51_coreplex_rtl_evaluation_v1p0\verilog\design\_EVAL_129.v 11.18 KB 2017/5/4 20:26:09
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135 sifive_E51_coreplex_rtl_evaluation_v1p0\verilog\testbench\Queue_17.v 11 KB 2017/5/4 20:26:13
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137 sifive_E51_coreplex_rtl_evaluation_v1p0\verilog\testbench\_EVAL_59_sim.v 10.92 KB 2017/5/4 20:26:11
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149 sifive_E51_coreplex_rtl_evaluation_v1p0\verilog\design\_EVAL_43.v 9.92 KB 2017/5/4 20:26:09
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153 sifive_E51_coreplex_rtl_evaluation_v1p0\verilog\design\_EVAL_153.v 8.98 KB 2017/5/4 20:26:09
154 sifive_E51_coreplex_rtl_evaluation_v1p0\verilog\testbench\_EVAL_139_sim.v 8.19 KB 2017/5/4 20:26:11
155 sifive_E51_coreplex_rtl_evaluation_v1p0\tests\rv64ui-add\program.elf 8.08 KB 2017/5/4 20:26:07
156 sifive_E51_coreplex_rtl_evaluation_v1p0\tests\rv64um-mul\program.elf 7.92 KB 2017/5/4 20:26:08
157 sifive_E51_coreplex_rtl_evaluation_v1p0\verilog\design\_EVAL_102.v 7.74 KB 2017/5/4 20:26:08
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