iic开发资料.tar.gz
所属分类:开发技术 > 硬件开发
文件大小:1.41 MB
上传日期:2022-05-29 11:35
MD5:8a15d2c370************a453165703
资源说明:i2c_latest,iic开发资料,分别有xilinx和altera例程。
本站所提供资源仅作为个人学习、交流使用,不可用于任何商业目的与用途。
# | 文件名称 | 大小 | 最后修改时间 |
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1 | i2c | 0 Bytes | 2019/8/20 20:36:27 |
2 | i2c\trunk | 0 Bytes | 2019/8/20 20:36:27 |
3 | i2c\trunk\sim | 0 Bytes | 2019/8/20 20:36:27 |
4 | i2c\trunk\sim\i2c_verilog | 0 Bytes | 2019/8/20 20:36:27 |
5 | i2c\trunk\sim\i2c_verilog\run | 0 Bytes | 2019/8/20 20:36:27 |
6 | i2c\trunk\sim\i2c_verilog\run\bench.vcd | 5.07 MB | 2002/6/15 15:37:11 |
7 | i2c\trunk\sim\i2c_verilog\run\run | 514 Bytes | 2007/4/6 17:02:38 |
8 | i2c\trunk\sim\i2c_verilog\run\ncverilog.log | 4.59 KB | 2002/6/15 15:37:11 |
9 | i2c\trunk\sim\i2c_verilog\run\ncverilog.key | 5 Bytes | 2002/6/15 15:37:11 |
10 | i2c\trunk\doc | 0 Bytes | 2019/8/20 20:36:27 |
11 | i2c\trunk\doc\src | 0 Bytes | 2019/8/20 20:36:27 |
12 | i2c\trunk\doc\src\I2C_specs.doc | 454 KB | 2003/7/3 23:21:23 |
13 | i2c\trunk\doc\i2c_specs.pdf | 206.51 KB | 2003/7/3 23:21:23 |
14 | i2c\trunk\rtl | 0 Bytes | 2019/8/20 20:36:27 |
15 | i2c\trunk\rtl\verilog | 0 Bytes | 2019/8/20 20:36:27 |
16 | i2c\trunk\rtl\verilog\i2c_master_byte_ctrl.v | 10.3 KB | 2009/1/20 4:29:26 |
17 | i2c\trunk\rtl\verilog\i2c_master_bit_ctrl.v | 20.63 KB | 2010/1/13 0:36:48 |
18 | i2c\trunk\rtl\verilog\timescale.v | 23 Bytes | 2001/9/24 20:21:51 |
19 | i2c\trunk\rtl\verilog\i2c_master_defines.v | 2.94 KB | 2001/11/5 19:59:25 |
20 | i2c\trunk\rtl\verilog\i2c_master_top.v | 9.82 KB | 2010/1/13 0:35:28 |
21 | i2c\trunk\rtl\vhdl | 0 Bytes | 2019/8/20 20:36:27 |
22 | i2c\trunk\rtl\vhdl\i2c_master_byte_ctrl.vhd | 12.33 KB | 2004/2/18 19:41:48 |
23 | i2c\trunk\rtl\vhdl\readme | 789 Bytes | 2002/12/1 6:25:47 |
24 | i2c\trunk\rtl\vhdl\tst_ds1621.vhd | 6.8 KB | 2001/9/24 20:21:51 |
25 | i2c\trunk\rtl\vhdl\i2c_master_bit_ctrl.vhd | 23.92 KB | 2010/6/6 17:46:45 |
26 | i2c\trunk\rtl\vhdl\I2C.VHD | 13.22 KB | 2001/9/24 20:21:51 |
27 | i2c\trunk\rtl\vhdl\i2c_master_top.vhd | 14.61 KB | 2010/1/13 0:25:35 |
28 | i2c\trunk\bench | 0 Bytes | 2019/8/20 20:36:27 |
29 | i2c\trunk\bench\verilog | 0 Bytes | 2019/8/20 20:36:27 |
30 | i2c\trunk\bench\verilog\wb_master_model.v | 5.44 KB | 2004/2/28 23:40:42 |
31 | i2c\trunk\bench\verilog\i2c_slave_model.v | 11.16 KB | 2006/9/4 17:08:51 |
32 | i2c\trunk\bench\verilog\spi_slave_model.v | 3.75 KB | 2004/2/28 23:32:55 |
33 | i2c\trunk\bench\verilog\tst_bench_top.v | 14.15 KB | 2006/9/4 17:08:51 |
34 | i2c\trunk\software | 0 Bytes | 2019/8/20 20:36:27 |
35 | i2c\trunk\software\include | 0 Bytes | 2019/8/20 20:36:27 |
36 | i2c\trunk\software\include\oc_i2c_master.h | 5.59 KB | 2001/11/22 18:02:19 |
37 | i2c\web_uploads | 0 Bytes | 2019/8/20 20:36:27 |
38 | i2c\web_uploads\index.shtml | 1.73 KB | 2009/3/10 21:32:02 |
39 | i2c\web_uploads\Block.gif | 7.9 KB | 2009/3/10 21:32:02 |
40 | i2c\web_uploads\i2c_rev03.pdf | 76.64 KB | 2009/3/10 21:32:02 |
41 | i2c\web_uploads\index_orig.shtml | 1.58 KB | 2009/3/10 21:32:02 |
42 | i2c\tags | 0 Bytes | 2019/8/20 20:36:27 |
43 | i2c\tags\rel_1 | 0 Bytes | 2019/8/20 20:36:27 |
44 | i2c\tags\rel_1\sim | 0 Bytes | 2019/8/20 20:36:27 |
45 | i2c\tags\rel_1\sim\i2c_verilog | 0 Bytes | 2019/8/20 20:36:27 |
46 | i2c\tags\rel_1\sim\i2c_verilog\run | 0 Bytes | 2019/8/20 20:36:27 |
47 | i2c\tags\rel_1\sim\i2c_verilog\run\bench.vcd | 5.07 MB | 2002/6/15 15:37:11 |
48 | i2c\tags\rel_1\sim\i2c_verilog\run\run | 597 Bytes | 2002/6/15 15:37:11 |
49 | i2c\tags\rel_1\sim\i2c_verilog\run\ncverilog.log | 4.59 KB | 2002/6/15 15:37:11 |
50 | i2c\tags\rel_1\sim\i2c_verilog\run\ncverilog.key | 5 Bytes | 2002/6/15 15:37:11 |
51 | i2c\tags\rel_1\doc | 0 Bytes | 2019/8/20 20:36:27 |
52 | i2c\tags\rel_1\doc\src | 0 Bytes | 2019/8/20 20:36:27 |
53 | i2c\tags\rel_1\doc\src\I2C_specs.doc | 454 KB | 2003/7/3 23:21:23 |
54 | i2c\tags\rel_1\doc\i2c_specs.pdf | 206.51 KB | 2003/7/3 23:21:23 |
55 | i2c\tags\rel_1\rtl | 0 Bytes | 2019/8/20 20:36:27 |
56 | i2c\tags\rel_1\rtl\verilog | 0 Bytes | 2019/8/20 20:36:27 |
57 | i2c\tags\rel_1\rtl\verilog\i2c_master_byte_ctrl.v | 10.03 KB | 2003/8/9 15:01:33 |
58 | i2c\tags\rel_1\rtl\verilog\i2c_master_bit_ctrl.v | 16.37 KB | 2003/8/9 15:01:33 |
59 | i2c\tags\rel_1\rtl\verilog\timescale.v | 23 Bytes | 2001/9/24 20:21:51 |
60 | i2c\tags\rel_1\rtl\verilog\i2c_master_defines.v | 2.94 KB | 2001/11/5 19:59:25 |
61 | i2c\tags\rel_1\rtl\verilog\i2c_master_top.v | 9.54 KB | 2003/9/1 18:34:38 |
62 | i2c\tags\rel_1\rtl\vhdl | 0 Bytes | 2019/8/20 20:36:27 |
63 | i2c\tags\rel_1\rtl\vhdl\i2c_master_byte_ctrl.vhd | 12.14 KB | 2003/8/9 15:01:33 |
64 | i2c\tags\rel_1\rtl\vhdl\readme | 789 Bytes | 2002/12/1 6:25:47 |
65 | i2c\tags\rel_1\rtl\vhdl\tst_ds1621.vhd | 6.8 KB | 2001/9/24 20:21:51 |
66 | i2c\tags\rel_1\rtl\vhdl\i2c_master_bit_ctrl.vhd | 16.77 KB | 2003/8/12 22:48:37 |
67 | i2c\tags\rel_1\rtl\vhdl\I2C.VHD | 13.22 KB | 2001/9/24 20:21:51 |
68 | i2c\tags\rel_1\rtl\vhdl\i2c_master_top.vhd | 12.66 KB | 2003/8/9 15:01:33 |
69 | i2c\tags\rel_1\bench | 0 Bytes | 2019/8/20 20:36:27 |
70 | i2c\tags\rel_1\bench\verilog | 0 Bytes | 2019/8/20 20:36:27 |
71 | i2c\tags\rel_1\bench\verilog\wb_master_model.v | 5.44 KB | 2002/3/17 18:26:38 |
72 | i2c\tags\rel_1\bench\verilog\i2c_slave_model.v | 10.54 KB | 2003/9/11 16:25:37 |
73 | i2c\tags\rel_1\bench\verilog\tst_bench_top.v | 12.67 KB | 2002/10/31 2:11:06 |
74 | i2c\tags\rel_1\software | 0 Bytes | 2019/8/20 20:36:27 |
75 | i2c\tags\rel_1\software\include | 0 Bytes | 2019/8/20 20:36:27 |
76 | i2c\tags\rel_1\software\include\oc_i2c_master.h | 5.59 KB | 2001/11/22 18:02:19 |
77 | i2c\tags\asyst_2 | 0 Bytes | 2019/8/20 20:36:27 |
78 | i2c\tags\asyst_2\rtl | 0 Bytes | 2019/8/20 20:36:27 |
79 | i2c\tags\asyst_2\rtl\verilog | 0 Bytes | 2019/8/20 20:36:27 |
80 | i2c\tags\asyst_2\rtl\verilog\i2c_master_byte_ctrl.v | 10.03 KB | 2003/8/9 15:01:33 |
81 | i2c\tags\asyst_2\rtl\verilog\i2c_master_bit_ctrl.v | 16.37 KB | 2003/8/9 15:01:33 |
82 | i2c\tags\asyst_2\rtl\verilog\timescale.v | 23 Bytes | 2001/9/24 20:21:51 |
83 | i2c\tags\asyst_2\rtl\verilog\i2c_master_defines.v | 2.94 KB | 2001/11/5 19:59:25 |
84 | i2c\tags\asyst_2\rtl\verilog\i2c_master_top.v | 9.54 KB | 2003/9/1 18:34:38 |
85 | i2c\tags\asyst_3 | 0 Bytes | 2019/8/20 20:36:27 |
86 | i2c\tags\asyst_3\rtl | 0 Bytes | 2019/8/20 20:36:27 |
87 | i2c\tags\asyst_3\rtl\verilog | 0 Bytes | 2019/8/20 20:36:27 |
88 | i2c\tags\asyst_3\rtl\verilog\i2c_master_byte_ctrl.v | 10.03 KB | 2003/8/9 15:01:33 |
89 | i2c\tags\asyst_3\rtl\verilog\i2c_master_bit_ctrl.v | 16.37 KB | 2003/8/9 15:01:33 |
90 | i2c\tags\asyst_3\rtl\verilog\timescale.v | 23 Bytes | 2001/9/24 20:21:51 |
91 | i2c\tags\asyst_3\rtl\verilog\i2c_master_defines.v | 2.94 KB | 2001/11/5 19:59:25 |
92 | i2c\tags\asyst_3\rtl\verilog\i2c_master_top.v | 9.54 KB | 2003/9/1 18:34:38 |
93 | i2c\tags\first | 0 Bytes | 2019/8/20 20:36:27 |
94 | i2c\tags\first\tst_ds1621.vhd | 6.8 KB | 2001/1/3 18:09:07 |
95 | i2c\tags\first\I2C.VHD | 13.22 KB | 2001/1/3 18:09:07 |
96 | i2c\branches | 0 Bytes | 2019/8/20 20:36:27 |
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